Monday, 27 February 2012

Counters


Counter is a sequential circuit which can go through a sequence of states on application of clock pulses. Counters cab be synchronous or asynchronous.
A counter having n flip-flops will have 2n states. Mod N counter consists of N states. To implement that it requires n flip-flops such that 2n≥N.
Difference between synchronous counters and asynchronous circuits:
  • In synchronous counters each flip-flop will have same clock signal
  • In asynchronous counter each flip-flop will get different clock. Clock for a flip-flop comes from output of some other flip-flop.
  • Synchronous counters are faster.
  • Asynchronous counters are slower, because previous flip-flop propagation delay will be added to clock signal of current flip-flop. Hence max. Frequency of operation reduces.
Except counters in all other sequential circuits, synchronous circuits are slower than asynchronous circuits.
Asynchronous counter:
Above figure shows asynchronous counter using T flip-flop. From the figure it can be observed that the clock signal to a flip-flop comes from previous T-flip-flop.
Since T inputs of all flip-flops are ‘1’, on each rising edge of clock flip-flop state changes. First flip-flop output Q0 changes state on each clock edge. But the output Q0 changes from 0 to 1 only for two clock cycles. Thus output of second flip-flop changes once for two clock pulses. Similarly the remaining third flip-flop output changes for every 4 clock cycles and 4th flip-flop output changes once for every 8 clock pulses.  Thus this will produce the required counter operation.
Asynchronous counters are slower because to change the state of last flip-flop, all previous stage flip-flops needs to change their state. If we assume all the flip-flop delays are same ‘tn’, then for a circuit having n flip-flops, delay is ntn. Thus maximum frequency of operation becomes 1/ntn.

Synchronous counter:
 
In synchronous circuit each flip-flop is driven by the same clock. The first flip-flop output Q0 changes on each clock edge. The second flip-flop output changes only when Q0 is ‘1’ (This is because Q0 is connected to second flip-flop T input). And this happens once for every two clock pulses. And the output of third flip-flop changes only when Q0Q1 outputs are 1’s. This happens only once for every four clock cycles.   The last flip-flop output Q3 changes only when Q0Q1Q2 changes to all 1’s. This happens once for every 8 clock cycles.
Down counter: In down counter, output of counter decrements for each clock edge. The states of counter will be 15, 14, 13 ….1, 0 for a 4-bit counter.
Up counter: In up counter, output of counter increments on each clock edge. The states of counter will be 0, 1, 2… 14, 15.
Up/Down counter will have a control signal, which makes a counter to count up or down depending on the control signal.
 BCD counter is a counter having 10 states. This is also called decade counter.


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