Sunday, 19 February 2012


Latches are not suitable for implementation of synchronous sequential circuits, because when clock input is active, the excitation input directly changes the output. Thus it becomes two combinational circuits connected back to back. Because of this the circuit may become unstable. To avoid this excitation input should only change the output at only single transition. This is done using flip-flops.
Flip-flops also store single bit of information.
Master- Slave SR flip-flop:  
  • When clk=’0’, master SR latch C is ‘1’ and S&R excitation inputs can change the master output. But C input of slave is ‘0’. So changes in S-R of slave (which are connected to outputs of master latch which are changing) latch can’t be reflected at output.
  • When clk=’1’, C input of master latch becomes ‘0’, hence it can’t respond to S-R inputs. Hence master latch output can’t change. C input of slave is ‘1’, so it can change state here.
  • Thus the total circuit changes state only at positive edge of clock. Thus it behaves as flip-flop.
 Below figure shows the operation of master slave flip-flop
-ve edge triggered flip-flop:
SR Flip-flop state diagram:
SR Flip-flop State Table:
SR Flip-flop excitation table: 
Characteristic equation:

Master Slave D Flip-flop:
  • When CLK=’0’, master latch is enabled. So any transition on D input causes changes in output. But Slave latch is not enabled since C input is ‘0’
  • When CLK=’1’ master latch disables and hence it holds its previous state value. And slave latch is enabled now, hence master output gets stored in slave latch. Thus in total it behaves as a positive edge triggered flip-flop.
State diagram:
State Table:
Excitation table:
Characteristic Equation:

Master-Slave JK Flip-flop:
Operation of JK flip-flop is similar to SR flip-flop, S is similar to J and R is similar to K. But when both J and K are asserted at the same time, output is toggled (i.e. complement of previous state).
State Diagram:
State Table:
Excitation table:
Characteristic equation:

T flip-flop:
When T input to flip-flop is ‘1’ then on every CLK edge (rising or falling), Flip-flop toggles its state.
State diagram:
State Table:
Excitation table: 
Characteristic equation:

Back                                            Contents                                                Next

No comments:

Post a Comment