Saturday, 18 February 2012

Latches


Latch is a memory element which stores a single bit of information
SR Latch:
SR latch is also called set-reset latch. There are two types of SR latches: NAND latch and NOR latch.
NAND Latch:
  • When Set S is low, Latch is set (So 1 is stored in it)
  • When Reset is low, Latch is reset (So 0 is stored in it)
  • When both the inputs are at ‘1’, then previous state is hold in latch
  • When both the inputs are low then, latch outputs Q and Q’ becomes ‘0’, which is contradictory to Q and complement of Q (Q’). And also the next state of flip-flop after changing the S or R input is unpredictable. Hence this input combination should not be applied to latch.
NOR Latch:
  • When Set S is high, Latch is set (So 1 is stored in it)
  • When Reset is high, Latch is reset (So 0 is stored in it)
  • When both the inputs are at ‘0’, then previous state is hold in latch
  • When both the inputs are high then, latch outputs Q and Q’ becomes ‘0’, which is contradictory to Q and complement of Q (Q’). And also the next state of flip-flop after changing the S or R input is unpredictable. Hence this input combination should not be applied to latch.
Gated SR Latch:
  
The functionality of SR Latch and Gated SR Latch are same. But Gated SR latch works only when CLK input is high. When clock input is low previous state of latch is hold. So the Latch operations are synchronized with clock.

D- Latch:
D latch acts as simply delay latch. When CLK is high, the input D is stored in Latch. When CLK is low previous state of latch is hold.

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