Friday, 23 March 2012

8085 bus timings and machine cycles

       Before continuing with bus timings and various machine cycles, Let us concentrate on what an instruction is and what are machine cycles and what is T-state.
      An instruction is a command given to processor to perform some data processing task. An instruction consists of Opcode and operand information (may be immediate data, or reference to operand). Opcode describes what operation needs to be performed by processor. To execute each instruction processor requires some machine cycles. These machine cycles are some basic processing steps to finish an instruction execution. For example to execute an instruction opcode needs to be fetched from memory and then data need to be read from memory. These kinds of operations are called machine cycles. To perform each machine cycle processor requires some no. of T-states. In each T-state microprocessor perform some micro operation of each machine cycle. For example to fetch opcode, processor needs to issue address to memory, and issue read signal, and opcode needs to be stored in instruction register from data bus, All these are some micro operations To perform these operations processor requires some T-states.
8085 microprocessor performs following machine cycles as a whole. All the instructions may not require all the machine cycles.  
  1. Opcode fetch
  2. Memory read
  3. Memory write
  4. I/O read
  5. I/O write
  6. Interrupt acknowledge
  7. Halt
  8. Hold
  9. Reset 
Opcode Fetch Machine Cycle:
Opcode fetch cycle is part of any instruction execution. In this machine cycle 8085 fetches opcode of instruction. The following are the sequence of actions that are performed by 8085 to fetch an opcode from memory. This machine cycle consists of 4 T-states.
  • 8085 places 16-bit address from PC on to the address bus (of course lower order address bus is multiplexed with data bus) and issues ALE pulse in first T-state (T1). This is used to de-multiplex the address and data bus. It also issues IO/M’ signal to ‘0’. This indicates that processor is performing memory related operation.
  • In second T-state (T2) processor issues RD’ control signal to memory. This enables memory to put data present at the address location given in previous T-state on to data bus. RD’ control signal is active for two clock pulses.
  • In T3 state memory places opcode on Data bus. Processor reads opcode present on data bus and de-asserts RD’ signal. Thus data bus goes into high impedance state.
  • In T4 state processor decodes instruction and necessary actions are performed.
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