Friday, 23 March 2012

Memory Read and Write, IO Read and write Machine cycles


Memory Read machine cycle:
This machine cycle is required when an operand is present in memory. This machine cycle requires three T-states. The following are the sequence of actions performed by microprocessor during this machine cycle.
  • In the first T-state (T1) 8085 places address on address bus and issues ALE signal. And also IO/M’ signal is made low, since it is memory related operation.
  • In the second T-state (T2), processor issues RD’ control signal to memory. In response to this memory places data on data bus.
  • In the third T-state (T3), processor reads data from data bus, and de-asserts RD’ signal.
Memory Write Machine cycle:
 This machine cycle is required when the results of operation needs to store in memory. This machine cycle requires three T-states. The following are sequence of actions performed by processor in this machine cycle.
  • In first T-state (T1), 8085 processor places 16- bit address on address bus and issues ALE signal. And also it makes IO/M’ signal to low, indicating it is memory related operation.
  • In second T-state (T2), processor places data to be written on data bus and asserts WR’ signal to the memory.
  • In the third T-state (T3), memory stores the data and processor de-asserts WR’ signal. 
IO read machine cycle:
This machine cycle is required, when data needs to be read from an input device. This machine cycle requires three T-states. The following are the sequence of actions performed by processor during this machine cycle.
  • In the first T-state (T1) 8085 places port address(for IO mapped addresses port address is 8-bit, but for memory mapped addresses IO device address is 16-bit, but reading from such is performed by memory read machine cycle) on address bus and issues ALE signal. And also IO/M’ signal is made high, since it is IO related operation.  
  • In the second T-state (T2), processor issues RD’ control signal to IO peripheral. In response to this input device places data on data bus.
  • In the third T-state (T3), processor reads data from data bus, and de-asserts RD’ signal.
IO write Machine cycle:
This machine cycle is required when data needs to be output to an output device. This machine cycle requires three T-states. The following are the sequence of actions performed by processor during this machine cycle.
  
  • In first T-state (T1), 8085 processor places 8-bit port address on address bus (for IO mapped addresses port address is 8-bit, but for memory mapped addresses, IO device address is 16-bit, but writing to such is performed by memory write machine cycle) and issues ALE signal. And also it makes IO/M’ signal to high, indicating it is IO related operation.
  • In second T-state (T2), processor places data to be written on data bus and asserts WR’ signal to the peripheral.
  • In the third T-state (T3), peripheral accepts the data and processor de-asserts WR’ signal.
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