Tuesday, 17 April 2012

Memory interfacing to 8085

8085 has 16 bit address bus; hence it can access 216 no. of memory locations, which is equal to 64KB memory.  For any microprocessor memory is required to store program as well as data. Since microprocessor doesn’t have on-chip memory, we need to connect it externally. So it requires addressing mechanism. The following are the steps involved in interfacing memory with 8085 processor.

  1. First decide the size of memory requires to be interfaced. Depending on this we can say how many address lines are required for it. For example if you want to interface 4KB (212) memory it requires 12 address lines. Remaining address lines can be used in address decoding.
  2. Depending on the size of memory required and given address range, construct address decoding circuitry. This address decoding circuitry can be implemented with NAND gates and/or decoders or using PAL (when board size is a constraint).
  3. Connect data bus of memory to processor data bus.
  4. Generate the control signals required for memory using IO/M’, WR’, RD’ signals of 8085 processor. 
Example:
Interface 4KB memory to 8085 with starting address A000H.
  1. 4KB memory requires 12 address lines for addressing as already mentioned. But 8085 has 16 address lines. Hence four of address lines are used for address decoding
  2. Given that starting address for memory is A000H. So for 4KB memory ending address becomes A000H+0FFFH (4KB) = AFFFH.
 A0-A11 address lines are directly connected to address bus of memory chip. A12-A15 are used for generating chip select signal for memory chip.
Address decoding circuit using 3X8 decoder:
A15 line is use for enabling 74x138 decoder chip. A12, A13, A14 lines are connected to 74X138 chip as inputs. When theses lines are 010 output should be ‘0’. This is provided at O2 pin of 74X138 chip.
Address decoding circuit using only NAND gates:
A15, A14, A13, A12 inputs should be 1010, for enabling the chip. So the circuit for this is as shown above.
Types of address decoding:
There are two types of address decoding mechanism, based on address lines used for generating chip select signal.
  1. Absolute decoding
  2. Partial decoding
Absolute decoding:
All the higher order lines of microprocessor, left after using the required signals for memory are completely used for generating chip select signal as shown in above example. This type of decoding is called absolute decoding.
Partial decoding:
Only some of the address lines of microprocessor left after using the required signals for memory are used for generating chip select signal. Because of this multiple address ranges will be formed. If total memory space is not required for the system then, this type of address decoding can be used. The advantage of this technique is fewer components are required for memory interfacing because of this board size reduces and in turn cost reduces.
Example:
Connect 512 bytes of memory to 8085
  1. For interfacing 512 bytes 9 address lines are required. So A0-A8 can be used to directly connect to address bus of memory.
  2. In the remaining A9-A15 for example only A15-A12 are used for generating chip select signal. A11-A9 are don’t care signals. 
Because of the don’t care signals the address range can be
0000 to 01FF
0200 to 03FF
0400 to 05FF
0600 to 07FF
0800 to 09FF
0A00 to 0BFF
0C00 to 0DFF
0E00 to 0FFF
Address decoding circuit:
 
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14 comments:

  1. How can we interface 3kb of ram with 8085 microprocessor

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    Replies
    1. Memory Size that can be interfaced will be in powers of 2. So you can connect either 2KB or 4KB memory. For interfacing 4KB memory you can refer to above example, in which the starting address for 4KB RAM is given as A000H, which can be changed to your own required starting address. In such a case the connections to 3 to 8 decoder inputs needs to be modified.

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  2. let, i want to write in memory..
    control signals
    wr'= 0
    rd'=1 (it is right?)
    io/m'=0
    NAND gives output 1 according to above inputs.if i am right WR' in 4kb memory(in fig) receives 1. wr' have to be 0 to enable write mode.. but output is 1. i am not getting it plz explain about that circles in input of NAND gate and memory.

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    Replies
    1. For memory write operation to memory 8085 issues WR'=0,IO/M'=0,Rd'=1 (Yes it's right). These are inverted and given as input to NAND gate(Observe that inputs of NAND gate are bubbled - circles). So both the inputs now become logic 1. hence NAND produces output '0', Which is correct logic level.

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  3. Here why a15 to a12 is given values 1010 . Can we give another value or not please explain

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    Replies
    1. Sorry for delay in replying...
      It is just an assumption that Memory starting address is A000H, So A15 to A12 is taken as 1010. If starting address of memory is 7000H, A15 to A12 will be 0111.

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  4. what be do in case of available ICs.

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  5. How can we interface 16k rom and 32k ram with 8085 microprocessor..??

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  6. It would be better if you show how unused address lines are connected in the decoding circuit for partial decoding mechanism

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  7. interface 4K*8 RAM to 8085 using 4K*4 RAM chip....how to interface ??

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