Saturday, 5 May 2012

8085 interrupts

An interrupt is a signal or condition that causes processor to stop its normal execution flow and makes it to jump to some other location for processing the interrupt.

8085 has 4 mask-able interrupts and 1 non-mask-able interrupts. Mask able interrupts can be disabled be DI instruction. Among four mask-able interrupts one is non-vectored interrupt, that is processor cannot go to a fixed location as in case of vectored interrupt, the external device which caused interrupts needs to specify the vector address.

8085 interrupt response process:
interrupts should be enabled by using EI instruction, then only processor responds to all mask able interrupts.
  • When microprocessor is executing a program, it checks for INTR line during execution of each instruction.
  • If INTR is high then processor completes executing the current instruction, disables the interrupts and sends a INTA signal
  • INTA is used by the external hardware to specify the restart instruction to processor( since INTR is a non-vectored interrupt).
  • When microprocessor receives the RST instruction, it saves PC content on stack and PC is loaded with the vector address.
  • Microprocessor executes the instructions at vector address.
  • The interrupts should be enabled if required in the ISR(interrupt service routine)
  • At the end of interrupt service routine, RET instruction loads the PC from the stack. So processor comes back to the instruction where it was interrupted previously.
Restart instructions:
These instructions are like software interrupts to 8085. When these instructions are executed processor vectors(jumps) to a specific location called restart location. The following list gives restart location for different RST instructions.
'n' value -- Vector location -- hex code
RST 0 -- 0000H -- C7
RST 1 -- 0008H -- CF
RST 2 -- 0010H -- D7
RST 3 -- 0018H -- DF
RST 4 -- 0020H -- E7
RST 5 -- 0028H -- EF
RST 6 -- 0030H --F7
RST 7 -- 0038H --FF
To get the vector location 'n' value is multiplied by 8 and the result is converted to hexadecimal notation. For example RST 3 instruction, multiply 3*8=24. 24 in hexadecimal notation is 18H. So vector address is 0018H.
8085 has 5 external interrupts. As already mentioned in this 4 are vectored interrupts and 1 is non-vectored interrupt.
RST 5.5, RST 6.5, RST 7.5, TRAP are vectored interrupts. INTR is non-vectored interrupt. TRAP is a non mask able interrupt.

Interrupt Priority:
when more than one interrupts occur at the same time, then processor responds to them according to the following priority
RST 7.5
RST 6.5
RST 5.5
INTR (lowest)

Interrupt vector locations:
TRAP – 0024H(it is same as RST 4.5)
RST 5.5 – 002CH
RST 6.5 – 0034H
RST 7.5 – 003CH
To get the vector location for RST interrupts, interrupt value is multiplied by 8 and the result is converted to hexadecimal notation. For example RST 5.5 instruction, multiply 5.5*8=44. 44 in hexadecimal notation is 2CH. So vector address is 002CH.

Trigger levels:
TRAP is level and edge triggered
RST 7.5 is positive edge triggered
RST 6.5, RST 5.5 are level triggered.

Masking of interrupts:
SIM instruction sets mask pattern for RST 5.5, RST 6.5, RST 7.5.
SIM instructions reads accumulator bit pattern and accordingly masks the interrupts. The bit pattern is shown in below figure. It also resets D flip-flop of RST 7.5 interrupt. And it also implements serial I/O.

Reading pending interrupts:
RIM instruction is used to read pending interrupts. After executing this instruction accumulator is loaded with the interrupt status signals. The pattern is shown in below figure. This instruction is also used to receive serial data.

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