Saturday, 22 September 2012

Introduction to VHDL

       VHDL stands for VHSIC(Very high speed integrated circuits) Hardware description language. In 1980's US Department of defense started VHSIC program. As part of this program many companies are involved in making High speed ICs. To describe their chips each company was using their own proprietary language. Because of this interfacing chips from different manufacturers is very difficult. Thus the need for a standard hardware description language was arrived. US DOD gave the responsibility of developing a standard HDL to three companies IBM, TI(Texas Instruments) and Intermetrics. The first VHDL standard was released in 1985. In 1987 IEEE standardized VHDL. In 1993 VHDL was updated and the new standard was released[1076-1993]. VHDL standard is being updated for every five years and the last update was in 2008[IEEE 1076-2008].

VHDL Module:
      VHDL module consists of two parts one is entity and the next is architecture. Entity declares the interface signals to the system, i.e. inputs and outputs to the system. Architecture defines the functionality of the system.
entity entity-name is
port(signal-name: mode signal-type;
signal-name: mode signal-type);
end entity-name;
       entity-name and signal-name can be any valid identifiers. Signal-type can be bit for scalar, bit_vector for vectors. Types of VHDL will be discussed later in this tutorial. Modes are the direction of defined ports. Ports can be inputs, outputs, inouts, linkage, or buffer type.
in – input port to the entity
out – output port to the entity.
inout – it acts as both input and output to the entity. Used o declare bidirectional signals like data bus in memories or processors.
Buffer – it also can be used as both input as well as output. But only one source can drive this port. But inout can be driven by two sources.
entity andor is
port(a, b, c, d: in std_logic; y: out std_logic);
end andor;
architecture architecture-name of entity-name is
signal declarations;
function definitions;
constant declarations;
procedure definitions;
type declarations;
component declarations;
end architecture-name;

         architecture defines the functionality of the desired system. Entity only defines the interface. Architecture and entity are bound by using the statement “architecture architecture-name of entity-name is”. An entity can have any number of architecture definitions. But at a time only one architecture will be bound to the entity. This can be done by using configuration statement, which will be discussed later.
       Architecture consists of declaration section before beginning the actual body where the system functionality definition is present. Intermediate signals that are going to be used in the architecture definition are declared. Functions and procedures that are being called in the architecture are defined. Then components used in architecture(in structural modeling) are declared. Similarly constants, and type declarations are also present. Architecture body consists of all concurrent statements. These statements can be signal assignment statements, process statements or component instantiations. Architecture body must be enclosed within the begin and end statements as shown in syntax.
architecture andor_arch of andor is
signal w1,w2:std_logic;
w1<= a and b;
w2<= c and d;
y<= w1 or w2;
end andor_arch;

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