Thursday, 21 March 2013

Basic Language Elements of VHDL



This chapter includes the discussion on basic language elements, data types, identifiers and operators. VHDL is case insensitive language. That is signal, SIGNAL, SigNal all are same.
Comments:
Comment lines increases the readability of program. And also it makes program simple to understand. In VHDL comment lines starts with “- -“ (two -) and end at the new line’\n’. That means there are no multi line comments in the VHDL
Example:
-- This is a comment line.
Identifiers:
Identifiers are the names given to variables, signals, constants, functions, procedures etc. In VHDL identifiers can use all upper case and lower case alphabets, digits (0-9) and special character _ (underscore). The rules for valid identifiers are
  1.  Identifier should start with a letter.
  2.  It should not end with underscore.
  3. Two consecutive underscores should not be used
Keywords:
Keywords are the reserved words by the language. These will have specific meaning in the language definition. These words should not be used as identifier names. Below table is the list of keywords.

Data Objects:
Signals, variables, constants are called data objects in VHDL. A data object can hold a value of data type specified.
 Constants: Constants can hold a single value of declared data type. This value can’t be changed during simulation. The syntax for constant declaration is shown below.
Syntax: constant constant-name: data type: =initial-value.
Example: constant no_of_bytes: integer: =8;
Variables: Variables can hold a single value of declared data type, whose value can be changed at any time. These are used inside process statements (behavioral design). Variable can store a value.
Syntax: variable variable-name: data-type: = initial value
Example: variable addrgen: std_logic_vector (7 downto 0): =”00000000”;
 Signals:  Signals can hold a value of declared data type, as long as there is some driving element for it. Else it can’t hold the value. It represents physical wire connectivity in the hardware.
Syntax: signal signal-name: data type: = initial value;
Example: signal w1:std_logic;
Data types:
Data type specifies the range and type of values that a data object in VHDL can be assigned.  VHDL has five types of data types.

Scalar type:
‘bit’ is a scalar data type which can have either 0 or 1. There are other types of scalar data types.
  1. Enumeration
  2. Integer
  3. Floating
  4. Physical
Enumeration type: Enumeration data type consists of set of user defined values.
Example:  type color is (RED, GREEN, BLUE);
Here ‘color’ is enumerated data type. A signal declared with type as color can hold any one of the specified three values RED, GREEN, BLUE.
Integer:
Integer can hold a specified range of integer values. By default integer range is – (2^31 -1) to (2^31-1). But the range can be defined explicitly.
Example: signal a: integer;   
Here ‘a’ will have the default range.
For limiting the range the following syntax should be used. In this first we need to define a type with the required range. Then we need to declare data objects with this type.
type bit4 in range 15 downto 0;
Signal a: bit4;
Here ‘a’ will have range 0 to 15;
Floating type:
Floating type can hold a specified range of real values.  The predefined floating point format is real. The range of real is -1.0E38 to +1.0E38
Example: signal a: real;
For limiting the range, we need to define user defined data types. This can be done as shown below.
type tmpr in range 1.20 to 40.5;
Signal a: tmpr;
Physical type:
Physical type represents some physical measurement like quantity, length, time etc. The only predefined physical data type is ‘time’.
Composite type:
Composite type holds collection of values. There are two types of composite values, arrays and records.
Arrays:
Arrays hold same type of values. The following are different ways of array type declaration.
Type type-name is array (a to b) of reqrd-data-type;   -- a<b
Type type-name is array (a downto b) of reqrd-data-type;   -- a>b
Type type-name is array (range-type) of reqrd-data-type;   
Type type-name is array (range-type range a to b) of reqrd-data-type;
Type type-name is array (range-type range a downto b) of reqrd-data-type;
Example:
Type memory is array (255 downto 0) of bit_vector (7 downto 0);
Signal data: memory;
Record:
Record type is collection of different data types, like structure in C language.
Example:
type abc is record
a: integer range 1 to 10;
b: real range 0.5 to 1.5;
c: time;
end record; 

Access type:
These are like pointers in C language. For example
Type memory is array (255 downto 0) of bit_vector (7 downto 0);
Type ptr_mem is access memory;
Here memory is of type array. Ptr_mem is pointer for type memory.
 File type:
File type is used to access files in the system. Syntax for this is shown below.
Type type-name is file of type-of-values-in-file;
Example: type testvect is file of std_logic_vector(7 downto 0);
Here testvect is file type and the file consists of values of type ‘std_logic_vector(7 downto 0)’.

Other types:
Std_logic type:
This is the most widely used scalar type in physical circuits. This is also of enumerated data type. This data type is defined in ieee library, in the package std_logic_1164. So when we use this package both these library and package should be included in the HDL description. This data type will have nine values, which can effectively represent physical voltage levels in digital circuits. In the case of bit data type, It can only have either ‘0’ or ‘1’. But a physical circuit can be undetermined state (if we assume logic 1 for 5V and logic 0 for 0V, then there may be a case where the voltage may be 2.5) which can’t be represented by the bit data type. So std_logic is the most useful data type.
Std_logic has the following values
‘0’- for strong ‘0’
‘1’- for strong ‘1’
‘X’ – for unknown
‘Z’ – for high impedance
‘U’ –for unassigned
‘-‘ –for don’t care
‘L’ – for weak zero
‘H’ –for weak one
‘W’ –for weak unknown
 
Example: signal a: std_logic;

For vector type signals (more than single wire or bus), we can use std_logic_vector type
Example: signal a: std_logic_vector (7 downto 0);
Here ‘a’ is a bus or vector consisting of 8 wires.

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