Wednesday, 6 March 2013

First VHDL Program

Let us start our first VHDL program with a simple AND-OR gate.

The above program describes and-or gate. The first statement “library ieee;” declares the library ieee. This library consists of all type definitions, functions, procedures which can be used in any VHDL program. Library consists of packages. The second line “use ieee.std_logic_1164.all” is the package clause. This statement includes the package ‘std_logic_1164’ package of ieee library and ‘.all’ makes all the types and definitions to be included in the program.

                Next is the entity declaration. ‘and -or’ gate consists of 4 inputs and one output. Let us assume that a, b, c, d are the inputs and y is the output.  Hence a, b, c, d are declared as inputs inside the port declaration statement and y is declared as output. Below figure shows the entity diagram. 

Next is the architecture definition. As already mentioned entity only defines the physical interface of the system. Architecture consists of the actual system definition.

Inside the architecture two intermediate signals w1, w2 are declared.  W1 is assigned with logical AND between a and b. W2 is assigned with logical AND between c and d. y is assigned with logical OR of w1 and w2. All these three statements inside begin and end statements of architecture are signal assignment statements. This style of description is called the dataflow level modeling.
                Once the program is written, we need to check whether the program is working functionally as expected or not. For this we need to write a test bench. Test bench is another VHDL program which applies inputs to this system (unit under test). Writing test bench will be discussed in the next chapters. After writing the test bench, we need to simulate the design. Simulation output can be seen in wave form format. Below figure is the simulated output for and-or gate.

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