Tuesday, 29 July 2014

Dataflow modelling in VHDL

Dataflow description describes how signals flow from the input to output of the system. That means it uses Boolean equations of the outputs for describing the system.  In this description style signal assignment statements are used for describing the system.

Signal declaration statement:

Syntax: signal signal-name : data-type;

The above statement shows syntax for signal declaration statement. Before using the signal-name in the architecture definition, it has to be declared. The signal can be declared inside the architecture, package or entity.


1. signal a: std_logic; here ‘a’ is declared as signal of type std_logic. Here ’a’ is a scalar.

2. signal count: std_logic_vector(7 downto 0); Here ‘count’ is declared as signal of type std_logic_vector of size 8-bit vector.

Signal assignment statements:

Syntax: signal-name <= value or expression;

‘<=’ is the signal assignment operator. Signal assignment statement can assign value or result of an expression. So the right side of signal assignment operator can be value or a valid VHDL expression.

  1. Sum <= a xor b; Here “a xor b” is expression. Value of this expression will be calculated and assigned to signal ‘sum
  2. Address<=”000100111”; this is multi bit assignment statement, used to assign a vector type signal.
  3. a <=’1’; this is a single bit assignment statement, used to assign a scalar type signal.
  4. signal count: std_logic_vector(7 downto 0); count is declared as vector of size 8 bits. To assign value to individual bits in the vector, the following syntax will be used.
               a. count(0) <= ‘1’; bit ‘0’ of count signal is assigned value ‘1’.
               b. a group of bits in the count can also be assigned a value.
               c. count(3 downto 0) <=”1001”;
     5.  It is also possible to assign hex-decimal number to a signal. count<=X”92”;   
          this statement assigns hex-decimal number 0x92 to signal ‘count’. 

Concurrent signal assignment:
When more than one signal assignment statements are written in the architecture body, then all of them execute concurrently. For example consider half-adder example
sum < = a xor b;
cout <= a and b;
Here ‘sum’ and ‘cout’ assignments execute parallel. Thus if any value of ‘a’ or ‘b’ is changed then both sum and ‘cout’ expression on right hand side gets executed simultaneously and result will be assigned to ‘sum’ and ‘cout’. 

There are three types of signal assignment statements.
  1. simple signal assignment statements
  2. conditional signal assignment statements
  3. selected signal assignment statements
Simple signal assignment statements:
Syntax: signal-name <= expression;
All the signal assignment statements mentioned above are simple signal assignment statements. They execute unconditionally whenever any of the signal in the right side of the expression changes.
sum <= a xor b;
y <= (a and b) or (c and d);

Conditional signal assignment statements:
signal-name      <=    value0 when condition1 else
                                value1 when condition2 else
                                valuen-1 when condition n else
The above statement assigns value1 to signal on the left hand side if condition 1 is true, else it assigns value2, if condition2 is true. If all the conditions are false then valuen will be assigned. During synthesis this statement results in priority multiplexer logic, which is shown in below figure.
y<=a0 when sel=’0’ else
‘y’ gets value of ‘a0’ when ‘sel’ signal is logic ‘0’, else it gets ‘a1’. The above statement functions as a 2x1 multiplexer.

Selected signal assignment statement:
with expression select
signal-name     <=     value1 when condition1
                                value2 when condition2
                                valuen when others;
In this statement first expression is evaluated. If the result of the expression matches with condition1, then value1 will be assigned to signal in the left hand side. If the result matches with condition2, then value 2 will be assigned. If the result doesn’t match with any of the conditions, then valuen will be assigned to the signal. Synthesizer will generate multiplexer type logic for this statement.
with sel select
y <=  d0 when “00”,
         d1 when “01”,
         d2 when “10”,
         d3 when “11”,
         ‘0’ when others;
when sel=”00” then ‘y’ gets value ‘d0’, when sel=”01” then ‘y’ gets value ‘d1’, when sel=”10” then ‘y’ gets value ‘d2’, when sel=”11” then ‘y’ gets value ‘d3’. If the ‘sel’ value doesn’t match with any of the values specified above, then ‘0’ will be assigned to ‘y’. This is specified by using ‘others’ keyword.
The above statement is a 4x1 multiplexer.

Delayed signal assignments
Signal assignment statements can be delayed. That is a value can be assigned to a signal after a specified duration. But these statements cannot be synthesized. These will be used only for simulation.
syntax: signal-name <= value after n ns;
Example: a <= b after 10 ns;
This statement assigns value of ‘b’ to ‘a’ after 10 ns. That is if value of ‘b’ is changed at 5ns time, it will be assigned to ‘a’ at 15ns time instant. So the signal is delayed by 10 ns.

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1 comment:

  1. Great work! when will you choose dataflow over the other modeling styles?