Wednesday, 17 September 2014

Structural modeling in VHDL

Structural modeling is used when complete hardware of the system being modeled is known. This modeling style consists of the components and their inter connection. The components which will be used in this description can be described in any other VHDL description style. 
                Structural modeling is used to implement hierarchical design concept. That is the entities already declared and defined can be used to implement a higher level entity.

In the above figure D, E, F and G are the entities already declared and defined. Entity B can be designed by making use of entities D and E, Similarly entity C can be designed by making use of F and G. A is the top level entity, which is making use of B and C entities.
To use a lower level module in a higher level module, we need to declare lower level module as a component in the higher level module. That is to use module ‘B’ in module ‘A’, we need to declare ‘B’ as a component in module ‘A’. The same applies to ‘C’. Again to use D & E modules in ‘B’ we need to declare D & E as components in module ‘B’.

Structural modeling constructs:
 Component declaration:
component component-name
                port (signal-name: mode signal-type;
                          signal-name: mode signal-type;
                         signal-name: mode signal-type);
end component;
Component declaration should match with entity of module, which is being declared as component.

Component instantiation:
To use a component, we need to instantiate it. Instantiation defines how ports of a component are being connected (mapped) to other components. There are two types of mappings, implicit mapping and explicit mapping. In implicit mapping, we need not specify the component ports, only the signal to which a port on component needs to be connected will be specified, in the order it is declared in the component declaration. In case of explicit mapping, port name of component and signal to which it is going to be connected are specified explicitly. Here order is not important.  
implicit mapping:
label: component-name port map(signal1,signal2,…….signal n);
explicit mapping:
label: component-name port map(port1=>signal1, port2=>signal2, ……., port n=>signal n);
In explicit port mapping, we will specify to which each signal will be mapped by using a ‘=>’ operator. If we want don’t want to connect particular port to any signal, we can use ‘OPEN’ keyword.
Example program:
Half adder design by making use of XOR and AND gate.
 To describe half adder in structural model, we need XOR and AND gate components. So first we need to describe XOR and AND gates.
XOR gate:
AND gate:
Half adder:
In the above program lines 6 to 9 shows declaration of “and2ip” component, lines 10 to 13 shows declaration of “xor2ip” component. Inside the architecture these components will be instantiated and these components will be connected as required for the circuit functionality using port map statements.
Line 15 shows implicit port mapping statement and line 16 shows explicit port mapping statement. Line 15 connects port ‘a’ of xor2ip component to port ‘a’, port ‘b’ of xor2ip component to port ‘b’ and port ‘c’ of xor2ip component to port ‘sum’ of top level entity “hadder_stru”.  In line 16, and2ip port ‘a’ is connected to port ‘a’, port ‘b’ of and2ip is connected to port ‘b’ and port ‘c’ of and2ip to ‘cout’ of top level entity “hadder_stru”.

For-Generate loop:
Sometimes it is required to create multiple instantiations of a particular component. In such situations for generate loop can be used.
label: for identifier in range generate
                concurrent statement;
end generate;
 For example consider 8-bit inverter design using 1-bit inverter. If we use normal component instantiation statements, we need to repeat it 8 times as shown below
U1: inv port map(a(0),y(0));
U2: inv port map(a(1),y(1));
U8: inv port map(a(7),y(7));
Instead of this we can use for – generate loop,
for i in 0 to 7
      U1: inv port map(a(i), y(i));
end generate;

It is better to design most widely used components in generic way. For example an n-bit inverter, which can be configured for a 8-bit inverter or 16-bit inverter, depending on the requirement. For this VHDL provides generic constants. We can assign values to these constants during instantiation, using generic mapping statement.
Generic declaration:
generic constants can be declared in entity prior to port declarations.
entity entity-name is
                generic(constant-name: constant-type;
                                constant-name: constant-type;
                                constant-name: constant-type);
                port (signal-name: mode signal-type;
                         signal-name: mode signal-type);
end entity-name;
Generic map statement:
label: component-name generic map(constant-name => value)
                                                 port map(signal1,signal2, … signal);
Example using generic:
Below program shows design of n-bit inverter
While using this component in other modules inside the architecture we can assign value to generic constant ‘n’. Below program shows 8-bit inverter, using above component. In this ‘n’ is mapped to value 8 using generic map statement in line 12.

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