Friday, 7 November 2014

Behavioral Modeling in VHDL

When behavior of the system is known, we can use behavioral description. For example, we know how a D flip-flop is going to function, i.e. when a clock edge comes, value on D is stored in flip-flop (which is given as output). Such behavior can be modeled using the behavioral description. Basic construct for behavioral modeling is process statement.
syntax:
Process(signal-name, signal-name, …… signal-name)
type declarations
constant declarations
function definitions
procedure definitions
begin
                sequential statements
                ………
                sequential statements
end process

‘Process’ is a concurrent statement, which executes concurrently with other process statements, and other concurrent statements like signal assignment, component instantiation statements. ‘Process’ can declare variable but not signals.  Variables holds state within a process, but not visible outside the process. Variable holds memory and doesn’t require drive, whereas signal cannot hold data and it needs driving source.
                Process statement consist of sensitivity list i.e. signals specified in the ‘( )’ parenthesis.  Process will be in suspended state initially. Whenever any signal in the sensitivity list changes the process resumes the execution and executes all the statements inside the process sequentially till end. The sensitivity list is optional for a process. Process statement without sensitivity list is used for writing test bench. All the statements inside the process are sequential statements.
                The below programs is D-flip-flop with asynchronous preset and clear inputs. We can observe the process sensitivity list has CLK, CLRb, PRb signals (All inputs except D). So if any of these signals changes the process gets executed. D flip-flop functionality is whenever clock edge arise the value of ‘D’ gets stored in the flip-flop. This functionality is described in line 18. CLK’event and clock=’1’ indicates rising edge.  CLRb and PRb  are asynchronous inputs. If CLRb is ‘0’ then flip-flop gets cleared irrespective of clock edge. If PRb is ‘0’ then flip-flop is preset to ‘1’ irrespective of clock edge. This functionality is described by lines 16 and 17 in the program. ‘D’ is not placed in sensitivity list, because even if D changes without the clock edge, flip-flop need not respond.

SEQUENTIAL STATEMENTS
All the statements used inside the process statement are sequential statements. The statements inside the process statement are variable assignment statements, branching statements and looping statements.
Variable assignment statement
syntax:
variable-name:= value;
‘:=’ is a variable assignment operator. Unlike signal assignment statement variable assignment statements execute sequentially.
Example:
variable a: std_logic;
a:=’1’;
The first statement is a variable declaration statement. the second statement assigns value ‘1’ to variable ‘a’.

IF statement
if statement:
syntax:
if expression then sequential – statement
end if;
If the result of expression is true the sequential statements inside the ‘if’ will be executed.
if-else statement:
syntax:
if expression then sequential – statement
else sequential – statement
end if;
If the result of expression is true the sequential statements inside the ‘if’ will be executed, otherwise statements in side else will be executed.
nested if statement:
syntax:
if expression then sequential – statement
elsif expression then sequential – statement
……
elsif expression then sequential – statement
else sequential – statement
end if;
nested if statement can be created by using elsif clause of VHDL. If the expression is true the statements inside if will be executed, else the next expression is evaluated and if the result is true statement inside it will be executed. If all the expressions result in false then statements inside the else will be executed. It is also possible to write nested if statement without else clause. nested if statement creates priority multiplex structure after synthesis.
Below program describes 4x2 priority encoder, by using nested if statement. 4x2 priority encoder will have 4 inputs A(0) to A(3). if A(3) is ‘1’ then irrespective of other inputs i.e. even if A(2) is ‘1’ or any other,  output will be “11”. If A(3) is ‘0’ and A(2) is ‘1’ then irrespective of other inputs output is “10”. If A(3) and A(2) are “00”, A(1) is ‘1’ then output is “01”. If A(3),A(2) and A(1) are “000”, A(0) is ‘1’ then output is “00”. If any of the inputs A(3 downto 0) is’1’ then GS (got something) will be ‘1’, else it will be ‘0’.  In the below program, line 10 shows the process sensitivity list. Priority encoder output should change whenever any of the inputs are changed. So all inputs A(3 downto 0) are put in sensitivity list.
Line ‘12’ shows if A(3) is ‘1’ then output Y is assigned “11” and GS assigned ‘1’ . If A(3) is ‘0’ then line 12 will not get executed, A(2) is checked in line 13. If A(2) is ‘1’ then output Y is “10” and GS is ‘1’, else A(1) is checked in line 14. If A(1) is ‘1’ then output Y is “01” and GS is ‘1’, else A(0) is checked in line 15. If A(0) is ‘1’ then output Y is “00” and GS is ‘1’, else output Y is ”00” and GS is ‘0’. Thus priority is already given to A(3), next A(2), next A(1), next A(0) by making use of nested if statement

CASE statement:
syntax:
case expression is
                when choices  =>  sequential-statement
                ……….
                when choices  =>  sequential statement
end case

case statement evaluates expression and if the result is matched with any of the choices, then statements corresponding to that choices executes. All possible results of the expression should be present in the choices. If all possible result cannot be specified explicitly, then we can use others, i.e. “when others => sequential statements”. Case statement results in multiplexer based design after the synthesis.
 

The above program shows description of a 4x1 multiplexer. Multiplexer will have 4 data inputs (din(3:0)), and 2 control inputs(selection inputs – sel(1:0)). Multiplexer output ‘y’ depends on all these inputs. So process will have “din, sel” in sensitivity list. The case statement is used here to describe multiplexer functionality. In line 12 case is used with ‘sel’ as expression. When sel=”00”, the output ‘y’ is assigned ‘din(0)’ in line 13. When sel=”01”, the output ‘y’ is assigned ‘din(1)’ in line 14. When sel=”10”, the output ‘y’ is assigned ‘din(2)’ in line 15. When sel=”11”, the output ‘y’ is assigned ‘din(3)’ in line 16. If ‘sel’ has any other value then output ‘y’ is assigned value ‘0’. 

LOOP statement:
syntax:
loop
                sequential statement
                …………
                sequential statement
end loop;
this loop statement is infinite loop. we can use ‘exit’ statement to come out of the loop.
FOR LOOP statement:
syntax:
for identifier in range loop
                sequential statement
                ………………
                sequential statement
end loop;
The identifier value gets incremented, after every iteration.  The identifier gets all the values specified in the range. This loop executes for the no. of times specified in the range.
example:
for I in 0 to 7 loop
                if (i<3) then a<=y(i);
                else a<=z(i);
                end if;
end loop;
In the above example, first it gets value ‘0’ in the first iteration. In the next iteration it gets value ‘1’ and so on. In the last iteration it gets value ‘7’, after that loop gets completed.
We can use next statement inside the loop, to bypass the statements available after the ‘next statement’ inside the loop, like continue in C.          
WHILE LOOP statement:
syntax:
while expression loop
                sequential statement
                …………
                sequential statement
end loop
First the expression is evaluated. As long as the expression results in true, the loop gets executed. If the expression results in false, loop exits.
 
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