Sunday, 30 November 2014

Writing VHDL Test Bench


Test bench is used to test a model of electronic system. VHDL can be used to model an electronic system. The modeling can be done in dataflow, structural, behavioral or in mixed model. For knowing about modeling please refer to earlier posts. Testing involves applying stimulus or test vectors to the system under test and observing the outputs of the system under test for correctness.

                The objective of test bench is to generate stimulus to test the system, apply them to system under test , monitor output for correctness and log the transactions in a human readable form. System under test can also be called as unit under test(UUT).  

The advantages of VHDL test bench are

1. VHDL has powerful constructs to model the concurrent nature of hardware. So VHDL can be used to generate stimulus interactively with UUT as if UUT is in its original operational environment.

2. VHDL test bench is portable. So any simulator which supports VHDL can simulate using the test bench.

3.Common language for modeling and testing UUT. So designer need not know two different languages for testing and modeling.

Architecture of test bench:

Test vector generator generates stimulus for UUT. This modules can also take outputs coming from the UUT to interactively change the stimulus. Verifier takes stimulus and responses from UUT and checks for correctness. Simple test bench will not have verifier modeled into it. So the designer should manually check the correctness of the UUT output.

Simple test bench format:

entity entity-name is

end entity-name;

architecture testbench-architecture-name  of entity-name is

UUT component declaration statement;

local signal declarations for interacting with UUT;

begin

                UUT: UUT instantiation;

                stimulus-gen: process

                begin

                                test vector generation;

                end process;

end testbench-architecture-name;

                entity of test bench will not have any port declaration statements. Architecture consists of component declaration statement of unit under test. local signal are declared for giving inputs and taking outputs from the unit under test. If any intermediate signals are required for generating test vectors they are also declared. Architecture body consists of instantiation statement of unit under test. All inputs and outputs of component under test are mapped to local signals declared earlier. Test vectors are generated and assigned to local signals mapped to inputs of unit under test, using any of the concurrent assignment statements. Simulation tools like Modelsim, Xilinx Isim, Active HDL can be used to view the waveforms.

Example test bench program:

Below program shows the VHDL program for AND, OR, NOR, NAND, XOR, XNOR gates.
Below program describes test bench for a logic gates module- the above VHDL program(unit under test). It consists of two inputs 'a', 'b' and outputs 'o_and', 'o_or', 'o_xor', 'o_xnor', 'o_nor', 'o_nand'. The outputs are AND, OR, XOR, XNOR, NOR, NAND gates respectively.

In the above program the 4th line shows, entity 'gates_tb' with no ports declared in it. The architecture consists of 'gates' component declaration-UUT(line 9).  line 13 shows the signal declaration statements, used to interface the UUT.  line 16 shows UUT component instantiation statement. line 18 consists of process definition, which generates test vectors. Line 20 assigns to 'a' value '0', 'b' value '0' at time t=0ns. Line 21 has a wait statement, which waits for 10ns of time. Line 22 at 10ns assigns value '1' to 'b', so this time a is '0', b is '1'. Line 23 is again a wait statement for 10ns duration. Line 24 at 20ns assigns value '0' to 'b' and value '1' to 'a'. Line 25 is again a wait statement, which waits for 10ns. Line 26 assigns value '1' to 'b' at 30 ns, so this time 'a' is '1' and 'b' is '1'.

If we run this test bench on a simulator, we will get a waveform, as shown in below figure.
 

You can observe the output for correctness by monitoring each and every gate output o_and, o_nand etc. This monitoring also can be done inside test bench. The above test bench doesn't have this provision.
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