Sunday, 14 June 2015

Decoders implementation in VHDL

Decoder is a combinational circuit with n inputs and 2n outputs, in which at a time only one output is active.
2 to 4 decoder:
2 to 4 decoder takes 2-bit binary data as input, and produces logic ‘1’ on its binary equivalent number line. For example if A1A0 is “10” then Y2 will be ‘1’ and remaining are ‘0’s. Below table shows the truth table.


This truth table can be used for behavioral modeling in VHDL. Below program shows the VHDL program for 2x4 decoder in behavioral modeling.
VHDL program for 2x4 decoder in behavioral modeling:

The Boolean equations for outputs Y3, Y2, Y1, Y0 are
Y3 = A1 . A0  -> this can be written as A1 and A0
Y2 = A1 . A0' -> this can be written as A1 and (not A0)
Y1 = A1'. A0  -> this can be written as (not A1) and A0
Y0 = A1' . A0'->this can be written as (not A1) and (not A0)
From the outputs, we can observe that each output is a minterm representation of corresponding inputs. So decoder is simply a minterm generator. These equations can be used for dataflow modeling in VHDL.
VHDL program for 2x4 decoder in dataflow modeling:


We can draw the hardware using the above Boolean equations. This can be used for structural modeling in VHDL.

VHDL program for 2x4 decoder in structural modeling:


The above three programs are tested using a test bench and the output is shown below



3 to 8 decoder:

3 to 8 decoder takes 3-bit binary data as input, and produces logic ‘1’ on its binary equivalent number line. For example if A2A1A0 is “100” then Y4 will be ‘1’ and remaining are ‘0’s. Below table shows the truth table.


 We can design a 3 to 8 decoder using two 2x4 decoders. The 2x4 decoder should have ‘enable’ signal. If ‘enable’ is ‘0’ then all outputs of 2x4 decoder will be 0’s, else it responds to inputs in the same manner as the above 2x4 decoder. Below figure shows 3x8 decoder using two 2x4 decoders


A2 is MSB and A0 is LSB. When A2 is ‘0’ top 2x4 decoder gets enabled and responds to other inputs A1 and A0. When A2 is ‘1’ only bottom 2x4 decoder gets enabled. Thus 3x8 decoder can be realized.

Below VHDL program implements 3x8 decoder using two 2x4 decoders.

The simulation results for the above program are shown below

BCD to 7-segment decoder

Above figure shows seven segment LED display. These are widely used in Digital clocks and at Traffic islands. BCD data can’t be displayed directly on this display. So a code converter is needed. This code converter takes BCD data and produces data in a format to display the corresponding BCD number.
 To display BCD number 1, b and c LEDs (shown in above figure) should glow and remaining should be in turn off state. Similarly for remaining numbers same technique is applied. The truth table for this is shown below.

Truth table:


VHDL program for BCD to 7-segment decoder:


above program is written in behavioral modeling using case statement. The input BCD code is given through a vector input ‘bcd’ of size 4. The output ‘seg7’ is a vector of size 7. seg7(6) is segment ‘segment a’, seg7(5) is ‘segment b’, seg7(4) is ‘segment c’, seg7(3) is ‘segment d’, seg7(2) is ‘segment e’, seg7(1) is ‘segment f’, seg7(0) is ‘segment g’. Below figure shows the simulation results of BCD to seven segment decoder.

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