Monday, 29 June 2015

Encoders implementation in VHDL


Encoder is a combinatorial logic circuit consisting of 2n input lines and produces n-bit output.
8 to 3 Priority encoder
The entity for the 8x3 priority encoder is shown below. It consists of 8 inputs and produces 3 outputs. For more information on encoders refer to my earlier post. 

DIN [7:0] is a 8 bit input vector, signifies 8 input lines to encoder. EN is enabling input; if it is ‘0’ all outputs DOUT, GS and EO all will be ‘0’, else DOUT[2:0] is 3-bit output representing binary equivalent of  active line in DIN[7:0], if more lines are active at the same time, then highest priority input will be encoded. Input DIN (7) will be highest and DIN (0) will be having lowest priority.  GS signifies got something; active when encoder is enabled and any one of the inputs DIN [7:0] is active. EO signifies enable output; active when encoder is enabled and none of the inputs are active. The truth table for the encoder is shown below.


VHDL program for 8x3 priority encoder:
‘idout’ is the intermediate signal to hold the encoded data. Behavioral modeling is used for implementing priority encoder. Line 17 to line 25 describes priority encoder structure. In the nested IF statement first ‘din (7)’ is tested then ‘din (6)’ and so on and last ‘din (0)’. So ‘din (7)’ will have highest priority and ‘din (0)’ will have least priority. At line 28 ‘en’ signal is checked; if it is ‘1’ then ‘idout’ signal is assigned to ‘dout’, This statement makes sure that output is encoded only when ‘en’ is ‘1’. Line 29 implements ‘gs’, which will be active when any of ‘din’ signals active (implemented with ‘or’ operator) and with ‘en’. Line 31 implements ‘eo’ enable out, which is active when none of the inputs din are active (implemented with OR operation and the result is inverted- effectively NOR) and with ‘en’. 

Simulation Results:


16 to 4 Priority encoder using 8x3 priority encoder


16 x4 priority encoder can be implemented by cascading two 8x3 priority encoders as shown in above figure. U1 encoder takes higher order 8 inputs DIN [15:8] of DIN [15:0]. Enable signal is connected to enable of U1. If any of the inputs in DIN [15:8] are active they are encoded by U1. If none of the inputs are active then EO (enable out) of U1 will be active which is connected to enable of U2. So the remaining inputs DIN [7:0] are encoded by U2. If none of the inputs of U2 are also active then EO (enable output) of U2 will be active and it is the EO of the 16x4 encoder. If any of the GS bits of U1 and U2 are active then 16x4 encoder Gs will become active. This is implemented by U6 OR gate. DOUT (0) is generated by OR of DOUT (0) of U1 and DOUT (0) of U2. This is because, let us assume input is DIN (15) is active then U1 output is “111”, so DOUT (0) of U1 is ‘1’, but U2 is disabled and output will be “000” so DOUT (0) of U2 is ‘0’. Now assume input is DIN (1) is active. Then U1 output will be “000”, so DOUT(0) of U1 is ‘0’, U2 is enabled  as no inputs to U1 are active and its output is “001”, so DOUT(0) of U2 is ‘1’. So DOUT (0) of 16x4 encoder can be obtained by OR operation of both DOUT (0) of U1 and DOUT (0) of U2. Similarly DOUT (2), DOUT (1). DOUT (3) is GS of U1, this is because if any of the inputs to U1 are active DOUT(3) is always ‘1’( for DIN(15) output is “1111”, DIN(8) output is “1000”, so GS can be treated as output DOUT(3) of 16x4 encoder). Below figure shows entity of a 16x4 encoder.
VHDL program for 16x4 priority encoder: 

The above program implements the 16x4 priority encoder by making use of 8x3 priority encoder. The above explanation holds good for this program implementation. U1, U2 are priority encoder instantiations. U3, U4, U5, U6 are 2 input OR gate instantiations.
Simulation results:

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