Sunday, 14 June 2015

VHDL Timing constructs


VHDL timing constructs are used by VHDL simulator during testing. These statements cannot be synthesized.
Wait statement:
Wait is sequential statement, which can be used inside process or procedure. It can suspend the process or procedure, until the condition for wake-up occurs. It will be used for synchronization of processes.
wait  on sensitivity list:
wait on sensitivity list suspends the process or procedure until a event occurs on one of the signals in the sensitivity list.
ex: wait on s(0), s(1);
This statement suspends process till any one of the signal s(0), s(1) changes  its value.
wait until condition:
 wait until the condition  suspends the process or procedure until the condition specified is satisfied.
ex: wait until s(0)='1';
This statement suspends process until s(0) gets value '1'.
wait for time_duration:
wait for statement suspends the process or procedure, until the specified time is elapsed.
ex: wait for 10 ns;
This statement suspends the process for 10 ns duration.
After statement:
syntax: signal assignment after time-duration;
This statement assigns the value to the signal on the left hand side after the specified time duration.
ex: a <= '0' after 20 ns;
a<='0' after t=20 ns;

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