Wednesday, 7 September 2016

Multiplexers implementation in VHDL

Multiplexer is a combinatorial circuit that selects one out of many inputs depending on the selection lines. For more information on multiplexers refer to my earlier post.
2x1 multiplexer:
2x1 multiplexer consists of 2 data inputs and one selection line. If selection line is ‘0’ then input D0 will be selected (i.e. output DOUT will be D0). If selection line is ‘1’ then input D1 will be selected (i.e. output DOUT will be D1).  
Below VHDL program implements 2x1 multiplexer in dataflow modeling.
















Boolean equation for 2x1 multiplexer is given by 
DOUT = D0 . SEL’ + D1. SEL
Line 13 in the above VHDL program describes the same Boolean equation.

4x1 multiplexer:
4x1 multiplexer consists of 4 data inputs D0, D1, D2, D3 and 2 selection lines SEL(1), SEL(0). The output DOUT will be D0 if SEL is “00”, D1 if SEL is “01”, D2 if SEL is “10”, D3 if SEL is “11”. Below figure shows the block box view of a 4x1 multiplexer.


The Boolean equation for 4x1 multiplexer is given by
DOUT = SEL(1)’. SEL(0)’. D0 + SEL(1)’.SEL(0).D1 + SEL(1).SEL(0)’.D2 + SEL(1).SEL(0).D3
Below VHDL program shows dataflow model of 4x1 multiplexer.

VHDL program for 4x1 multiplexer:


In the above program 4x1 multiplexer also consists of enable input. If enable input is ‘1’ then only the operation of 4x1 multiplexer will be present, else output DOUT will be ‘0’ irrespective of inputs DIN(0),DIN(1),DIN(2),DIN(3) and SEL(1), SEL(0) inputs.
Line 12 implements 4x1 multiplexer using ‘WITH SELECT’ statement. ‘iy’ is intermediate signal which gets data inputs (din [3:0]) mapped to it based on the selection inputs ‘sel [1:0]’. signal ‘iy’ is assigned to output ‘dout’ only when enable ‘en’ is HIGH else output is ‘0’. The simulation results for this program are shown below.


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