Parity
bits are extra bits added to information bits so that a code word is formed
which can be used for error detecting or correcting. To obtain a minimum
distance 2 code, we add one parity bit.
There are two types of parity. The extra bit added is '1', if there are
odd number of 1's in the information bits called even parity. The extra bit
added is '1', if there are even number of 1's in the information bits called
odd parity.

__Parity generator:__

The
above table shows the truth table of parity generators. After simplification
using K-Maps, we get the following equations for odd and even parity generation
circuit.

odd
parity = I3 xnor I2 xnor I1 xnor I0

even parity = I3
xor I2 xor I1 xor I0

Below figure
shows the logic circuit implementation.

Below figure shows VHDL program for
parity generator

line 13 shows the XOR operation on
all input bits. This will result in even parity bit generation as already
mentioned in Boolean equation. line 15 simply performs not operation of even
parity generation, which means it's an odd parity generation. This is
equivalent to XNOR operation on the input bits. Below figure shows the
simulation results for parity generator.

__Parity checking:__

For odd parity checking, the no. of
bits in the received code word should be odd, otherwise it results in odd
parity error. For even parity checking, the no. of ones in the received code
word should be even, otherwise it results in even parity error. Below table
shows truth table for parity checker

The
Boolean equation for the parity checker functions are

odd
parity error = C3 xnor C2 xnor C1 xnor C0

even parity error
= C3 xor C2 xor C1 xor C0

Below figure
shows logic circuit implementation

Below figure
shows the VHDL program for parity checking.

Here line 13
performs even parity error checking as already mentioned in the Boolean
equation. Line 15 performs odd parity error checking, which is equivalent to
XNOR operation on the input bits. Below figure shows simulation results for
parity checker.

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